One-Day Workshop on “LLM for Chip Design”

The Department of Electronics and Communication Engineering, Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya (SCSVMV),

successfully conducted a One-Day Workshop on “LLM for Chip Design”, bringing together AI-driven methodologies and VLSI workflows.

The session was delivered by Dr. Sundararaman Rajagopalan, Hardware Design Consultant, who provided deep insights into how Large Language Models are transforming modern chip-design pipelines.

Key Technical Takeaways 🔸 Introduction to Verilateral, a tool for linting and structural analysis 🔸 Deep dive into lint errors, common categories, and their impact on design quality 🔸 Hands-on exposure to simulation frameworks where LLM-generated RTL was tested using cocotb 🔸 Overview of LLMs, GPTs and their architectural foundations 🔸 Practical hands-on session: Parameterized N-bit Counter Design using Verilog

श्रीचन्द्रशेखरेन्द्रसरस्वतीविश्वमहाविद्यालयः
Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya

One-Day Workshop on “LLM for Chip Design”

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